1. Field of the Invention
This invention relates to a latch circuit and a flip-flop circuit having a voltage level converting function and, more particularly, to a latch circuit and a flip-flop circuit having a voltage level converting function which are used in LSI operative with multiple power sources.
2. Description of the Prior Art
There are conventional LSI chips each having multiple power sources which partly share circuits in the chip to save power consumption. For example, a combinational logic circuit operative with a normal voltage VDD and a combinational logic circuit operative with a voltage VDDL lower than VDD are incorporated in a single LSI chip. In this type of LSI, it is necessary to convert the voltage level between the combinational logic circuit operative with the low voltage VDDL and the combinational logic circuit operative with the normal voltage VDD. That is, voltage level converter circuits are required. It is undesirable to locate such voltage level converter circuits in distant positions in the LSI chip because power consumption by the voltage level converter circuits themselves results in losing the power consumption decreasing effect by using two power sources in the chip. Therefore, it is believed to centralize the voltage level converter circuits near a flip-flop. Such a flip-flop circuit including voltage level converter circuit is usually called voltage level converting flip-flop circuit.
FIG. 15 shows a master slave type flip-flop circuit MSF of a usual type. The master slave type flip-flop circuit MSF includes a master latch circuit ML and a slave latch circuit SL. These master latch circuit ML and slave latch circuit SL are configured to pass data from a input terminal D and to output it from an output terminal Q when an input from a clock input terminal CLK is HIGH. When the input from the clock input terminal CLK is LOW, they function to hold data at the moment when the input rises to LOW. The signal input into the clock input terminal CLK of the master latch circuit ML shown in FIG. 15 is an inverted clock signal/CK. As a result, the master latch circuit ML exhibits a pass-through status for permitting data to pass through when the clock signal CK is LOW and exhibits a hold status for holding data when the clock signal CK is HIGH. In contrast, the signal input into the clock input terminal CLK of the slave latch circuit SL is a clock signal CK. As a result, the slave latch circuit SL exhibits a pass-through status for permitting data to pass when the clock signal CK is HIGH and exhibits a hold status for holding data when the clock signal CK is LOW. That is, the entirety of the master slave type flip-flop circuit MSF behaves as an edge trigger type flip-flop.
FIG. 16 through FIG. 18 show some examples of voltage level converting flip-flops made by combining a voltage level converter circuits with the master slave type flip-flop circuit MSF shown in FIG. 15. In FIG. 16, a voltage level converter circuit VC is located adjacent to the front end of the master slave type flip-flop MSF. In FIG. 17, the voltage level converter circuit VC is located adjacent to the rear end of the master slave type flip-flop MSF. In FIG. 18, the voltage level converter circuit VC is located adjacent to the read end similarly to the voltage level converting flip-flop shown in FIG. 17. The voltage level converting flip-flop circuit shown in FIG. 18 is different from the circuit of FIG. 17 in that an inverted output terminal/Q is provided at the output of the slave latch circuit SL and that the voltage level converter circuit VC uses an output signal from the inverted output terminal/Q. Therefore, the voltage level converter circuit VC shown in FIG. 18 includes an input terminal IN1 for introducing a signal from the output terminal Q of the slave latch circuit SL and an input terminal IN2 for introducing a signal from the inverted output terminal/Q of the same slave latch circuit SL.
In the voltage level converting flip-flop circuits referred to above, holding of data and conversion of the voltage level are executed independently, and it results in requiring more elements, hence requiring a larger circuit area, and hence slowing down the operation speed. Additionally, the voltage level converter circuit VC requires a power sufficient for operating independently, and results in increasing the entire power consumption.
Especially in the voltage level converting flip-flop circuit shown in FIG. 16, since it performs flip-flop operation after conversion of the voltage level, both the voltage level converter circuit VC and the master slave type flip-flop circuit MSF must be driven by the normal voltage VDD, and this invites a large power consumption. Additionally, since the master slave type flip-flop circuit MSF operates with the normal voltage VDD, it is a bar against a decrease in voltage for the clock signal CK. That is, the clock signal CK had to be operated with the normal voltage VDD and not with the lower voltage VDDL.
In contrast, in the voltage level converting flip-flops shown in FIGS. 17 and 18, voltage level conversion is done after flip-flop operation. Therefore, voltages of the input data signal ID and the clock signal CK could be decreased. That is, it was possible to activate the master slave type flip-flop circuit MSF with the lower voltage VDDL and to activate the voltage level converter circuit VC with the normal voltage VDD or with the normal voltage VDD and the lower voltage VDDL. However, there still remains the problem that the operation speed becomes slower because the entirety of the master slave type flip-flop circuit MSF operates with the lower voltage VDDL.
Another flip-flop circuit having a voltage level converting function is shown also in "1997 Symposium on VLSI Circuits Digest of Technical Papers, pp.97-98", for example. Here is shown is the flip-flop circuit shown in FIG. 22. As shown in FIG. 22, the flip-flop circuit is configured to introduce clock signals CK and input data signals ID changing within a low voltage VDDL from the left side of the drawing sheet and to release output data signal OD changing within the normal voltage VDD from the right side of the drawing sheet.
The flip-flop circuit shown in FIG. 22 requires that the threshold voltage in precharge p-type MOS transistors P1' and P2' be higher than those of the other MOS transistors to prevent the problem that, when the threshold voltage of the p-type MOS transistors P1' and P2' is low, these p-type MOS transistors P1' and P2' fail to become completely OFF even when the clock signal CK is HIGH, and result in leaving a leak current LC to flow. For example, focusing at the p-type MOS transistor P1', when the clock signal CK is HIGH, the p-type MOS transistor P1' must become completely OFF to cut a node X from the power source of the voltage VDD. However, when the threshold voltage of the p-type MOS transistor P1' is low, it does not become completely OFF even when the clock signal CK becomes HIGH, and a leak current LC flows from the power source of the voltage VDD to the node X. The same applies also to the p-type MOS transistor P2'. If the stationary leak current LC flows while the clock signal CK is HIGH in this manner, the power consumption increases, and the operation speed is slowed down. For these reasons, the threshold voltage of the p-type MOS transistors P1' and P2' must be set high.
In order to keep the threshold voltage high, conventional techniques relied on applying a threshold control voltage VWELL to the substrate of these p-type MOS transistors P1' and P2'. However, the use of the threshold control voltage VWELL invited the need for at least three kinds of voltage sources to activate the flip-flop circuit. That is, because the circuit required the voltage VDD for activating MOS transistors such as p-type MOS transistors P1' and P2' and the voltage VDDL for generating clock signals CK, etc., and for activating an inverter INV1' in addition to the threshold control voltage VWELL, totally three power sources different in voltage value had to be used.
On the other hand, there was a method for controlling the threshold voltage of the p-type MOS transistors P1' and P2' in a step of ion implantation during the manufacturing process of an integrated circuit. However, this approach resulted in making a MOS transistors having different threshold voltages within a single integrated circuit and hence resulted in increasing steps of the manufacturing process and the production cost.